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TMC
24A01/24A02/24A04/24A08/24A16
1K/2K/4K/8K/16K-bit Serial EEPROM for Low Power
Data Sheet
OVERVIEW
The TMC 24A01/24A02/24A04/24A08/24A16 serial EEPROM has a 1,024/2,048/4,096/8,192/16,384-bit 2 capacity, supporting the standard I CTM-bus serial interface. It is fabricated using TMC's most advanced CMOS technology. It has been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its major feature is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the TMC 24A01/24A02/24A08/24A16 is its support for fast mode and standard mode.
FEATURES
I2C-Bus Interface * * Two-wire serial interface Automatic word address increment * Operating Characteristics * Operating voltage -- 1.8 V to 5.5 V Operating current -- Maximum write current: < 3 mA at 5.5 V -- Maximum read current: < 200 A at 5.5 V -- Maximum stand-by current: < 5 A at 5.5 V * Operating temperature range -- - 25C to + 70C (commercial) -- - 40C to + 85C (industrial) * Operating clock frequencies -- 100 kHz at standard mode -- 400 kHz at fast mode * Electrostatic discharge (ESD) -- 5,000 V (HBM) -- 500 V (MM) Packages * 8-pin DIP, SOP, TSSOP, and SOT 25
EEPROM * * * * * *
* *
1K/2K/4K/8K/16K-bit (128/256/512/1,024/2,048-byte) storage area 16-byte page buffer Hardware-based write protection for the entire EEPROM (using the WP pin) EEPROM programming voltage generated on chip 1,000,000 erase/write cycles 100 years data retention
24AXXL Marking means Lead Free product 24AXXG Marking means Green product
1
SDA
Start/Stop Logic
HV Generation Timing Control
WP
Control Logic
SCL
Slave Address Comparator
Word Address Pointer
Row decoder
A0 A1 A2
EEPROM Cell Array 128 x 8 bits 256 x 8 bits 512 x 8 bits 1024 x 8 bits 2048 x 8 bits
Column Decoder
Data Register
DOUT and ACK
Figure 3-1. Block Diagram
2
VCC
WP
SCL SDA
SOT25 SCL 1 2 3 5 WP
TMC24A02/08/16
TMC 24A01/24A02 24A04/24A08/24A16
Vss SDA
4
Vcc
A0
A1
A2
VSS
NOTE:
The TMC 24A01/24A02/24A04/24A08/24A16 is available in 8-pin DIP, SOP, TSSOP, and SOT 25 package.
Figure 3-2. Pin Assignment Diagram
Table 3-1. Pin Descriptions Name A0, A1, A2 Type Input Description Input pins for device address selection. To configure a device address, these pins should be connected to the VCC or VSS of the device. These pins are internally pulled down to VSS. Ground pin. Bi-directional data pin for the I2C-bus serial data interface. Schmitt trigger input and open-drain output. An external pull-up resistor must be connected to VCC. Typical values for this pull-up resistor are 4.7 k (100 kHz) and 1 k (400 kHz). Schmitt trigger input pin for serial clock input. Input pin for hardware write protection control. If you tie this pin to VCC, the write function is disabled to protect previously written data in the entire memory; if you tie it to VSS, the write function is enabled. This pin is internally pulled down to VSS. Single power supply. Circuit Type 1
VSS SDA
- I/O
- 3
SCL WP
Input Input
2 1
VCC
-
-
NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3.
3
A0, A1, A2, WP
SCL
Noise Filter
Figure 3-3. Pin Circuit Type 1
Figure 3-4. Pin Circuit Type 2
SDA Data Out
VSS Noise Filter
Data In
Figure 3-5. Pin Circuit Type 3
4
FUNCTION DESCRIPTION
I C-BUS INTERFACE The TMC 24A01/24A02/24A04/24A08/24A16 supports the I C-bus serial interface data transmission protocol. The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a pull-up resistor that is located somewhere on the bus. Any device that puts data onto the bus is defined as the "transmitter" and any device that gets data from the bus is the "receiver." The bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. Using the A0, A1, and A2 input pins, up to eight TMC 24A01/24A02 (four 2 TMC24A04, two for TMC24A08, one for TMC24A16) devices can be connected to the same I C-bus as slaves (see Figure 3-6). Both the master and slaves can operate as transmitter or receiver, but the master device determines which bus operating mode would be active.
2 2
VCC
VCC
SDA SCL Slave 1 Bus Master (Transmitter/ Receiver) MCU To VCC or VSS To VCC or VSS To VCC or VSS To VCC or VSS TMC24A02 Tx/Rx A0 A1 A2 Slave 2 TMC 24A02 Tx/Rx A0 A1 A2 Slave 3 TMC24A02 Tx/Rx A0 A1 A2 Slave 8 TMC 24A02 Tx/Rx A0 A1 A2
NOTES: 1. The A0 does not affect the device address of the TMC 24A04 2. The A0, A1 do not affect the device address of the TMC 24A08. 3. The A0, A1, and A2 do not affect the device address of the TMC 24A16.
Figure 3-6. Typical Configuration (16 Kbits of Memory on the I2C-Bus)
5
I2C-BUS PROTOCOLS
2 Here are several rules for I C-bus transfers:
-- A new data transfer can be initiated only when the bus is currently not busy. -- MSB is always transferred first in transmitting data. -- During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High.
2 The I C-bus interface supports the following communication protocols:
* * *
Bus not busy: The SDA and the SCL lines remain High level when the bus is not active. Start condition: Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains High level. All bus commands must be preceded by a start condition. Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains High level. All bus operations must be completed by a stop condition (see Figure 3-7).
~ ~
SCL
~ ~
SDA
Start Condition
Data or Data ACK Valid Change
Stop Condition
Figure 3-7. Data Transmission Sequence * Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited. ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it successfully received the eight bits of data (see Figure 3-8). But the slave does not send an ACK if an internal write cycle is still in progress. In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode.
*
6
Master SCL Line
Bit 1
Bit 9
Data from Transmitter
ACK from Receiver ACK
Figure 3-8. Acknowledge Response From Receiver * Slave Address: After the master initiates a Start condition, it must output the address of the device to be accessed. The most significant four bits of the slave address are called the "device identifier". The identifier for the TMC 24A01/24A02/24A04/24A08/24A16 is "1010B". The next three bits comprise the address of a specific device. The device address is defined by the state of the A0, A1 and A2 pins. Using this addressing scheme, you can cascade up to eight TMC 24A01/24A02 or four TMC 24A04 or two TMC 24A08 or one TMC 24A16 on the bus (see Table 3-2 below). The b1 for TMC 24A04 or the b1, b2 for TMC 24A08 or the b1, b2, b3 for TMC24A16 are used by the master to select which of the blocks of internal memory (1 block = 256 words) are to be accessed. The bits are in effect the most significant bits of the word address. Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the R/W bit is "1", a read operation is executed. If it is "0", a write operation is executed.
*
Table 3-2. Slave Device Addressing Device Device Identifier b7 TMC24A01/24A02 TMC24A04 TMC24A08 TMC24A16 1 1 1 1 b6 0 0 0 0 b5 1 1 1 1 b4 0 0 0 0 b3 A2 A2 A2 B2 Device Address b2 A1 A1 B1 B1 b1 A0 B0 B0 B0
W R/W Bit
b0 R/W R/W R/W R/W
NOTE: The B2, B1, B0 correspond to the MSB of the memory array address word.
7
BYTE WRITE OPERATION In a complete byte write operation, the master transmits the slave address, word address, and one data byte to the TMC 24A01/24A02/24A04/24A08/24A16 slave device (see Figure 3-9).
Start
Slave Address
Word Address
Data
Stop
A C K
A C K
A C K
Figure 3-9. Byte Write Operation Following the Start condition, the master sends the device identifier (4 bits), the device address (3 bits), and an R/W bit set to "0" onto the bus. Then the addressed TMC 24A01/24A02/24A04/24A08/24A16 generates an ACK and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is written into the word address pointer of the TMC 24A01/24A02/24A04/24A08/24A16. When the TMC 24A01/24A02/24A04/24A08/24A16 receives the word address, it responds by issuing an ACK and then waits for the next 8-bit data. When it receives the data byte, the TMC 24A01/24A02/24A04/24A08/24A16 again responds with an ACK. The master terminates the transfer by generating a Stop condition, at which time the TMC 24A01/24A02/24A04/24A08/24A16 begins the internal write cycle. While the internal write cycle is in progress, all TMC 24A01/24A02/24A04/24A08/24A16 inputs are disabled and the TMC 24A01/24A02/24A04/24A08/24A16 does not respond to additional requests from the master.
8
PAGE WRITE OPERATION The TMC 24A01/24A02/24A04/24A08/24A16 can also perform 16-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 15 additional bytes. The TMC 24A01/24A02/24A04/24A08/24A16 responds with an ACK each time it receives a complete byte of data (see Figure 3-10).
Start
Slave Address
Word Address (n)
Data (n)
Data ( n + 15)
Stop
A C K
A C K
A C K
A C K
A C K
Figure 3-10. Page Write Operation The TMC 24A01/24A02/24A04/24A08/24A16 automatically increments the word address pointer each time it receives a complete data byte. When one byte has been received, the internal word address pointer increments to the next address and the next data byte can be received. If the master transmits more than 16 bytes before it generates a stop condition to end the page write operation, the TMC 24A01/24A02/24A04/24A08/24A16 word address pointer value "rolls over" and the previously received data is overwritten. If the master transmits less than 16 bytes and generates a stop condition, the TMC 24A01/24A02/24A04/24A08/24A16 writes the received data to the corresponding EEPROM address. During a page write operation, all inputs are disabled and there is no response to additional requests from the master until the internal write cycle is completed.
9
POLLING FOR AN ACK SIGNAL When the master issues a stop condition to initiate a write cycle, the TMC 24A01/24A02/24A04/24A08/24A16 starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device. To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address. As long as the TMC 24A01/24A02/24A04/24A08/24A16 remains busy with the write operation, no ACK is returned. When the TMC 24A01/24A02/24A04/24A08/24A16 completes the write operation, it returns an ACK and the master can then proceed with the next read or write operation (see Figure 3-11).
Send Write Command
Send Stop Condition to Initiate Write Cycle
Send Start Condition
Send Slave Address with R/W bit = "0"
No ACK = "0" ?
Yes Start Next Operation
Figure 3-11. Master Polling for an ACK Signal from a Slave Device
10
HARDWARE-BASED WRITE PROTECTION You can also write-protect the entire memory area of the TMC 24A01/24A02/24A04/24A08/24A16. This method of write protection is controlled by the state of the Write Protect (WP) pin. When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored. The TMC 24A01/24A02/24A04/24A08/24A16 will acknowledge slave and word address, but it will not generate an acknowledge after receiving the first byte of the data. Thus the write cycle will not be started when the stop condition is generated. By connecting the WP pin to VSS, the write function is allowed for the entire memory. These write protection features effectively change the EEPROM to a ROM in order to prevent data from being overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on the bus, but data bytes are not acknowledged. CURRENT ADDRESS BYTE READ OPERATION The internal word address pointer maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either read or write) was to the address "n", the next read operation would access data at address "n+1". When the TMC 24A01/24A02/24A04/24A08/24A16receives a slave address with the R/W bit set to "1", it issues an ACK and sends the eight bits of data. The master does not acknowledge the transfer but it does generate a Stop condition. In this way, the TMC 24A01/24A02/24A04/24A08/24A16 effectively stops the transmission (see Figure 3-12).
Start
Slave Address
Data
Stop
A C K
N O A C K
Figure 3-12. Current Address Byte Read Operation
11
RANDOM ADDRESS BYTE READ OPERATION Using random read operations, the master can access any memory location at any time. Before it issues the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. This operation is performed in the following steps: 1. The master first issues a Start condition, the slave address, and the word address to be read. (This step sets the internal word address pointer of the TMC 24A01/24A02/24A04/24A08/24A16 to the desired address.) 2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed by another slave address, with the R/W bit set to "1". 3. The TMC 24A01/24A02/24A04/24A08/24A16 then sends an ACK and the 8-bit data stored at the desired address. 4. At this point, the master does not acknowledge the transmission, but generates a stop condition instead. 5. In response, the TMC 24A01/24A02/24A04/24A08/24A16 stops transmitting data and reverts to its stand-by mode (see Figure 3-13).
Start
Slave Address
Word Address
Start
Slave Address
Data (n)
Stop
A C K
A C K
A C K
N O A C K
Figure 3-13. Random Address Byte Read Operation
12
SEQUENTIAL READ OPERATION Sequential read operations can be performed in two ways: as a series of current address reads or as random address reads. The first data is sent in the same way as the previous read mode used on the bus. The next time, however, the master responds with an ACK, indicating that it requires additional data. The TMC 24A01/24A02/24A04/24A08/24A16 continues to output data for each ACK it receives. To stop the sequential read operation, the master does not respond with an ACK, but instead issues a Stop condition. Using this method, data is output sequentially with the data from address "n" followed by the data from "n+1". The word address pointer for read operations increments all word addresses, allowing the entire EEPROM to be read sequentially in a single operation. After the entire EEPROM is read, the word address pointer "rolls over" and the TMC 24A01/24A02/24A04/24A08/24A16 continues to transmit data for each ACK it receives from the master (see Figure 3-14).
Start
Slave Address
Data (n)
Data (n + x)
~ ~
A C K
A C K
A C K
N O A C K
Figure 3-14. Sequential Read Operation
13
ELECTRICAL DATA
Table 3-3. Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Output voltage Operating temperature Storage temperature Electrostatic discharge Symbol VCC VIN VO TA TSTG VESD Conditions - - - - - HBM MM Rating - 0.3 to + 7.0 - 0.3 to + 7.0 - 0.3 to + 7.0 - 40 to + 85 - 65 to + 150 5000 500 Unit V V V
C C
V
Table 3-4. D.C. Electrical Characteristics (TA = - 25C to + 70C (C), - 40C to + 85C (I), VCC = 1.8 V to 5.5 V) Parameter Input low voltage Input high voltage Input leakage current Output leakage current Output low voltage Symbol VIL VIH ILI ILO VOL VIN = 0 to VCC VO = 0 to VCC IOL = 0.15 mA, VCC = 1.8 V IOL = 2.1 mA, VCC = 2.5 V Supply current Write ICC1 ICC2 Read ICC3 ICC4 Stand-by current ICC5 ICC6 VCC = 5.5 V, 400 kHz VCC = 1.8 V, 100 kHz VCC = 5.5 V, 400 kHz VCC = 1.8 V, 100 kHz VCC = SDA = SCL = 5.5 V, all other inputs = 0 V VCC = SDA = SCL = 1.8 V, all other inputs = 0 V Conditions SCL, SDA, A0, A1, A2 Min - 0.7 VCC - - - - - - - - - - Typ - - - - - - - - - - - - Max 0.3 VCC - 10 10 0.2 0.4 3 1 0.2 60 5 1 A A mA Unit V V A A V
14
Table 3-4. D.C. Electrical Characteristics (Continued) (TA = - 25C to + 70C (C), - 40C to + 85C (I), VCC = 1.8 V to 5.5 V) Parameter Input capacitance Symbol CIN Conditions 25 C, 1MHz, VCC = 5 V, VIN = 0 V, A0, A1, A2, SCL and WP pin 25 C, 1MHz, VCC = 5 V, VI/O = 0 V, SDA pin Min - Typ - Max 10 Unit pF
Input/output capacitance
CI/O
-
-
10
Table 3-5. A.C. Electrical Characteristics (TA = - 25C to + 70C (C), - 40C to + 85C (I), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions VCC = 1.8 to 5.5 V (Standard Mode) Min External clock frequency Clock high time Clock low time Rising time Falling time Start condition hold time Start condition setup time Data input hold time Data input setup time Stop condition setup time Bus free time Data output valid from clock low (note) Noise spike width Write cycle time FCLK tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF tAA tSP tWR - - - SDA, SCL SDA, SCL - - - - - Before new transmission - - - 0 4 4.7 - - 4 4.7 0 0.25 4 4.7 0.3 - - Max 100 - - 1 0.3 - - - - - - 3.5 100 5 VCC = 2.5 to 5.5 V (Fast Mode) Min 0 0.6 1.3 - - 0.6 0.6 0 0.1 0.6 1.3 - - - Max 400 - - 0.3 0.3 - - - - - - 0.9 50 5 ns ms kHz s Unit
NOTES: 1. Upon customers request, up to 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available. 2. When acting as a transmitter, the TMC 24A01/24A02/24A04/24A08/24A16 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition.
15
tF SCL tSU:STA SDA In tLOW
tHIGH
tR
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tAA SDA Out
tBUF
Figure 3-15. Timing Diagram for Bus Operations
~ ~
SCL
~ ~ ~ ~
SDA WORDn
8th Bit
ACK
~ ~
tWR Stop Condition Start Condition
Figure 3-16. Write Cycle Timing Diagram
16
Package Information
Plastic DIP Outline Dimensions
8-pin DIP (300mil) Outline Dimensions
A B 1 8 5 4
H C D E . G
=
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 355 240 125 125 16 50 3/4 295 335 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 375 260 135 145 20 70 3/4 315 375 15
Package Information
SOP Outline Dimensions
8-pin SOP (150mil) Outline Dimensions
A 1
8
5 B 4
C
C' G D E .
H
=
Symbol A B C C D E F G H a
Dimensions in mil Min. 228 149 14 189 53 3/4 4 22 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 244 157 20 197 69 3/4 10 28 12 10
Package Information
Carrier Tape Dimensions
D
E .
P0
P1
t
W C
B0
D1
P
K0 A0
SOP 8N Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 12.0+0.3 -0.1 8.00.1 1.750.1 5.50.1 1.550.1 1.5+0.25 4.00.1 2.00.1 6.40.1 5.200.1 2.10.1 0.30.05 9.3
Package Information
0-8 #8 #5
6.40 0.15
#1
#4
+ 0.10
0.125 - 0.05
3.10 MAX 0.15
1.20 MAX
0.10 MAX
0.65
+ 0.05 - 0.06
0.25
NOTES: 1. Dimensions are in millimeters.
8-TSSOP Package Dimensions
0.60
+ 0.15 - 0.10
8-TSSOP
4.40 0.10

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